1. Field of the Invention
The present invention relates to electronic circuits and more specifically to a method and system for an on chip measurement of duty cycle for an unknown clock signal.
2. Discussion of the Related Art
In the manufacturing of electronic components there is a need for measuring electrical signal parameters. By comparing the measured parameters with the expected values, the accurate operations of the components can be detected. So during fabrication process an accurate and innovative circuit can be designed using these techniques.
The measurement of a clock duty cycle is one of the essential signal parameter that needs to be analyzed. The duty cycle of a clock signal is a ratio of an on time to a total time period of a clock cycle. Integrated circuits rely on clock generators to provide the clock signal. The clock generators can include a phase locked loop (PLL) device or an oscillator.
The duty cycle of high frequency clocks obtained from a PLL system is very critical in terms of obeying the timing constraints in the applications. In the case of Double Data Rate (DDR) applications, where both the positive and negative edges of the clock are used, the duty cycle assumes even more importance.
The duty cycle in synchronous digital systems is extremely critical, when logic is synchronous to both the rising and falling edges of the clock. Even a slight error in the duty cycle can create a major difference in the speed of the system clock and thereby causing a significant impact on the performance of the designed circuit. For instance, a duty cycle error of just 5% can cause the system clock to run at a maximum speed that can be 10% lower than the desired maximum speed. Further, many circuits require a specific duty cycle for the clock signals to provide an optimal performance. Therefore, it is very essential to measure an accurate duty cycle for a circuit.
The duty cycle of the clock signal also depends on several other factors such as temperature, loading, circuit design, etc. Therefore, to properly account for the affects that vary the duty cycle, an accurate measurement of the duty cycle during normal operation is necessary.
Off chip measurement of the duty cycle of a high frequency clocks would not be accurate because of the contribution of the additional buffers required to drive these signals in the real world.
Therefore, there is a need for a novel on-chip duty cycle measurement technique for accurately measuring the duty cycle of an unknown clock signal. The novel technique employs a robust logic for enhancing the measurement capabilities with respect to supply voltages, processes and temperature variations.